MT47H128M4 is a DDR2 SDRAM memory module from the MT47H series. It uses a 4n-bit prefetch architecture, supports programmable CAS latency, supports 4/8-bit burst length, adjustable data output drive strength, has a 64ms, 8192-cycle refresh cycle, and supports JEDEC clock jitter specifications.
This Micron datasheet provides detailed information on three 512 Mb DDR2 SDRAM parts: MT47H128M4, MT47H64M8 and MT47H32M16. It covers organization, package options, voltage requirements, temperature ranges, and command timing.
The document includes functional block diagrams, pin assignments, electrical ratings, timing parameters, and ODT timing for power‑down modes, helping designers integrate these memory devices into commercial, industrial or automotive systems.
| Organization (MT47H128M4) | 32 M × 4 × 4 banks |
|---|---|
| Organization (MT47H64M8) | 16 M × 8 × 4 banks |
| Organization (MT47H32M16) | 8 M × 16 × 4 banks |
| Core Voltage (Vpp / Vdd) | 1.8 V ±0.1 V |
| I/O Standard | JEDEC‑standard 1.8 V SSTL_18‑compatible |
| Package (x16) | 84‑ball FBGA, 8 mm × 12.5 mm |
| Package (x4, x8) | 60‑ball FBGA, 8 mm × 10 mm |
| Industrial Temperature Range | 40 °C to 95 °C |
| Automotive Temperature Range | -40 °C to 105 °C |
| Commercial Temperature Range | 0 °C to 85 °C |
The devices operate at a core voltage of 1.8 V ±0.1 V.
MT47H128M4 is organized as 32 M × 4 × 4 banks, MT47H64M8 as 16 M × 8 × 4 banks, and MT47H32M16 as 8 M × 16 × 4 banks.