This document discusses the configuration and specifications of the 64Mb x4, x8, x16 SDRAM products produced by Micron Technology, Inc. The products are PC66, PC100, and PC133 compliant, fully synchronous, with internal pipelined operation, and the column address can be changed every clock cycle.
The Micron 64 Mb SDRAM family provides high‑speed synchronous operation in three configurations: 16 Mbit × 4, 8 Mbit × 8 and 4 Mbit × 16, each organized as a quad‑bank DRAM. The devices operate from a single +3.3 V supply and support PC66, PC100 and PC133 memory standards.
Key features include fully registered signals on the positive clock edge, programmable burst lengths (1, 2, 4, 8 or full page), auto‑precharge and self‑refresh modes, and LVTTL‑compatible I/O. The datasheet provides functional block diagrams, pin descriptions, timing tables, command definitions and initialization procedures.
| Package | 54‑pin TSOP II (400 mil) |
|---|---|
| Supply Voltage | +3.3 V ±0.3 V |
| Operating Temperature (Commercial) | 0 °C to +70 °C |
| Operating Temperature (Industrial) | -40 °C to +85 °C |
| Refresh Count | 4 K |
| Supported Burst Lengths | 1, 2, 4, 8, full page |
It operates from a single +3.3 V supply with a tolerance of ±0.3 V.
The devices support programmable burst lengths of 1, 2, 4, 8, or a full‑page burst.