A Micron technical note that provides design guidelines for implementing GDDR6, GDDR6N, and GDDR6 Automotive memory devices.
This design guide explains the architecture and key features of Micron's GDDR6 memory family, including the standard graphics part as well as the networking (GDDR6N) and automotive variants. It covers bandwidth capabilities, pin configurations, prefetch architecture, and the command‑address packetized bus.
The note also gives practical recommendations for signal integrity, power delivery, layout, PCB stack‑up, and channel options. Topics such as VPP supply, VREFC/VREFD settings, POD I/O buffers, and decoupling strategies are discussed to help designers achieve reliable high‑speed operation.
| Data pins | 32 |
|---|---|
| Channel configuration | Two independent x16 channels (or single x32 pseudo‑channel) |
| Prefetch length | 16n |
| Number of banks | 16 |
| Maximum data rate | 14 Gb/s (up to 20 Gb/s demonstrated) |
| Supported densities | 8 Gb and 16 Gb parts |
| VPP supply voltage | 1.8 V |
| Default VREFC level | 0.7 × VDDQ |
GDDR6 uses a 16n prefetch length.
GDDR6 provides 32 data pins.
The VPP supply for GDDR6 is 1.8 V.
The default VREFC level is 0.7 × VDDQ.