User guide for Altera's Interlaken MegaCore Function implementing Interlaken Protocol v1.2 for FPGA design with parameter settings, functional description…
This document provides detailed instructions for using the Altera Interlaken MegaCore Function, which implements the Interlaken Protocol Specification, Revision 1.2. It covers design flows, parameter settings, functional descriptions, and signal interfaces for FPGA implementations. The function supports various lane configurations and data rates on Stratix IV GT and GX devices, with features including flow control, low overhead framing, and integrity checking. It includes simulation and hardware verification guidance, as well as resource utilization data for different configurations.
| Supported Lane Rates | 3.125 to 10.3125 Gbps (Stratix IV GT), 3.125 to 6.375 Gbps (Stratix IV GX) |
|---|---|
| Supported Number of Lanes | 4, 8, 10, 12, and 20 |
| Raw Bandwidth | 12.50 Gbps to 127.50 Gbps |
It implements the Interlaken Protocol Specification, Revision 1.2.
Lane rates from 3.125 to 10.3125 Gbps.
Up to 127.50 Gbps raw bandwidth.
It provides Avalon-ST interfaces on the transmit and receive datapaths.