Xilinx Spartan-3E Libraries Guide for HDL Designs

About this manual

This guide describes the primitive and macro design elements that make up the Xilinx Unified Libraries for the Spartan‑3E FPGA architecture. It includes VHDL and Verilog instantiation and inference code examples for each element.

The document is organized by functional categories such as Arithmetic Functions, Clock Components, I/O Components, RAM/ROM, and Slice/CLB primitives. It also explains attributes, constraints, and provides links to additional Xilinx documentation and support resources.

What's inside

• About this Guide
• Conventions
• Functional Categories
• Attributes and Constraints
• Arithmetic Functions
• Clock Components
• I/O Components
• RAM/ROM
• Slice/CLB Primitives

Frequently asked questions

What does the Spartan‑3E Libraries Guide describe?

It describes the primitive elements available for Xilinx Spartan‑3E FPGA devices.

Where can I find additional documentation for Spartan‑3E?

Additional documentation can be found on the Xilinx website at http://www.xilinx.com/literature.

How are attributes applied to primitives?

Attributes are properties associated with a device architecture primitive that affect its functionality and are conveyed via generic maps in VHDL or defparams in Verilog.