Pericom PI6C2509-133 Low-Noise PLL Clock Driver Datasheet

This datasheet shows the pin definition of a certain model of IC, including the pin name, function, voltage, connection pin, etc.


Pericom PI6C2509-133 Low-Noise PLL Clock Driver Datasheet - cover page
Brand
Pericom
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
5
File format
PDF
File size
230 KB
Published
07 August, 2012
Updated
30 September, 2023
MD5 checksum
1BD051A0F9C8A1B9EBC9078660AAFA87

About this manual

The Pericom PI6C2509-133 is a low-noise, phase-locked loop (PLL) clock driver featuring nine clock outputs. It is specifically designed to meet the PC133 SDRAM Registered DIMM specification and supports operating frequencies up to 150 MHz.

What's inside

  • Product Features
  • Logic Block Diagram
  • Functional Table
  • Pin Functions
  • DC Specifications
  • AC Specifications
  • Package Mechanical Information

Specifications

Operating Frequency25 MHz - 150 MHz
Supply Voltage3.0V - 3.6V
Operating Temperature0°C to 70°C
Package TypePlastic 24-pin TSSOP (L)
Number of Outputs9 Clock Outputs

Frequently asked questions

What is the maximum operating frequency?

The device supports an operating frequency up to 150 MHz.

How many clock outputs does this driver provide?

It provides nine clock outputs, distributed as five for one bank and four for another.

Can the PLL be bypassed?

Yes, by strapping AVcc to ground, the PLL is bypassed and CLK_IN is buffered directly.

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