PERICOM PI74SSTU32866 Manual

Update: 01 October, 2023

The PI74SSTU32866 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity. It is designed for 1.7 V to 1.9 V VDD operation and supports DDR2-533/400. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RST) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR-II DIMM load, and meet SSTL_18 specifications. The error (QERR) output is 1.8 V open-drain driver.

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MD5 Checksum: AE9A0A1DE855CF184C5A555D49EF71AE

Publication date: 04 January, 2012

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PDF Link: PERICOM PI74SSTU32866 Manual PDF