This application note provides information about how to configure the general purpose timers (GPTs) integrated in the SPEAr3xx embedded MPU family
This document provides instructions on configuring the general purpose timers (GPTs) integrated into the SPEAr3xx embedded microprocessor unit (MPU) family. It details how to read free-running timer counters and configure various clock sources for these timers.
The note also addresses specific technical issues, such as unpredictable counter values when clocks are asynchronous and a software workaround involving three consecutive reads. Additionally, it describes and proposes a solution for the status register interrupt bit clear issue reported during the Puppy Linux project.
| Counter width per channel | 16-bit counter register |
|---|---|
| GPT clock sources | PLL3 (48MHz) or PLL1/OSCI/HCLK/PCLK prescaler |
| System tick generation interval | usually every 10 ms |
Reading the counter three times and checking if the difference between consecutive reads is within an expected maximum value.
Select PLL1 as the CNT_Clk source using the PRPH_CLK_CFG register.