This document is an application note that provides guidelines for PCB layout design for SPEAr600. SPEAr600 is a member of the SPEAr family of 32-bit embedded MPUs, featuring dual ARM926 cores, an external DDR2 memory interface, and a full set of powerful on-chip peripherals.
The document is an application note titled AN2797 designed to guide engineers in creating successful PCB layouts for the SPEAr600 device. The SPEAr600 is a 32-bit embedded MPU featuring dual ARM926 cores running at up to 333 MHz, packaged as a 23 x 23 mm PBGA420 with a 1 mm ball pitch.
The note details specific guidelines for power integrity and the DDR memory interface. It recommends a minimum of 6 PCB layers with closely spaced power/ground plane pairs and specifies low-inductance layouts for decoupling capacitors, such as using 0402 package sizes. Additionally, it covers signal routing requirements for data signals, USB interfaces, and external clock connections to ensure proper operation.
The SPEAr600 is a 23 x 23 mm PBGA420 device with a 1 mm ball pitch that features dual ARM926 cores running at up to 333 MHz.
A minimum of 6 layers is necessary for the PCB stack up.
All traces should have an impedance of 55 Ohm + 10%.