This application note describes how to extract the correct IBIS model from the SPEAr3xx IBIS library for signal integrity simulation in the application PCB.
This document is intended for hardware developers using the SPEAr3xx embedded MPU in target designs. It explains that IBIS models are mandatory for signal integrity simulation in application PCBs, particularly for high-speed interfaces like DDR2, to ensure the layout does not introduce functional or timing issues. The provided models are organized in a library where each model corresponds to a specific operating mode of the I/O pads.
The note details how to extract the correct model from the library by reading specific register settings or knowing the operating mode. It covers model selection for the PL_CLK & PL_GPIO interfaces, the DDR interface, and the USB interface, providing tables that correlate register bit values to specific model group names.
This document explains how to extract the correct IBIS model from a library for signal integrity simulation of SPEAr3xx applications.
The IBIS models provided for SPEAr3xx are organized in a model library named sp300_v3.ibs.
The operating modes are defined by a proper setting of two registers: DDR_PAD and MEMCTL_AHB_SET_02.