This application note describes how to configure the SPEAr3xx multi-port memory controller (MPMC) to use different types of DDR and DDR2 memories and tune the parameters in accordance with JEDEC requirements and the flexibility available in the application.
The document provides instructions on configuring the Multi-Port Memory Controller (MPMC) found in the SPEAr3xx embedded MPU family. It details how to interface with external DDR or DDR2 memory devices, ensuring compliance with JEDEC requirements.
The guide covers an overview of the SPEAr3xx architecture and its memory controller ports, followed by a technical comparison between DDR1 and DDR2 technologies. It includes specific programming instructions for configuring the MPMC for different memory parts and tuning delay lines for reading from and writing to DRAM.
| Max Clock Frequency | 333 MHz |
|---|---|
| Data Rate | 667 MT/sec |
| Supported Memory Types | DDR and DDR2 |
The memory controller supports frequencies up to 333 MHz.
The system achieves a data rate of 667 MT/sec.