AN2674 is an application note about SPEAr3xx, which introduces the PCB layout guidelines for SPEAr3xx, including power integrity, DDR memory interface, USB signals, GPIO/CLD signals and external clock.
This document serves as a technical guide for designing printed circuit board (PCB) layouts for the SPEAr3xx microcontroller family. It focuses on ensuring power integrity and signal quality for high-speed interfaces. Key areas addressed include the creation of low-impedance power delivery networks, proper placement of decoupling capacitors, and specific routing rules for DDR memory and USB signals.
| Device Family | SPEAr3xx |
|---|---|
| Package Type | LFBGA289 |
| Ball Pitch | 0.8 mm |
| Microprocessor Core | ARM926 |
| Maximum Frequency | 333 MHz |
| Memory Interface | DDR2 |
| Minimum PCB Layers | 6 layers |
| Recommended Capacitor Package | 0402 |
| Recommended Capacitance | 100 nF or larger |
| Recommended Dielectric | X7R or X5R |
| Signal Trace Width | 4 mil to 5 mil |
| Signal Trace Spacing | 4 mil to 5 mil |
| DDR Signal Separation | 10 mils |
A minimum of 6 layers is necessary to support the required signal trace characteristic impedances and power plane capacitance/inductance.
The 0402 package size is recommended to minimize mounting inductance and free up board space for more capacitors.
Vias should be placed on the side of the capacitor lands, not the ends, and connected with a wide trace.
X7R or X5R dielectric is recommended; Y5V dielectric should not be used for mid-frequency applications.