IS41C16256 and IS41LV16256 are high-performance CMOS dynamic random access memories. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41C16256 and IS41LV16256 ideal for use in 16 and 32-bit wide data bus systems. These features make the IS41C16256 and IS41LV1626 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. IS41C16256 and IS41LV16256 are packaged in 40-pin 400mil SOJ and TSOP (Type II).
This document is a technical datasheet for the ISSI IS41C16256 and IS41LV16256 devices. These are high-performance 262,144 x 16-bit CMOS Dynamic Random Access Memory (DRAM) chips featuring accelerated cycle access EDO Page Mode.
The datasheet details the electrical characteristics, timing parameters, and functional descriptions for both commercial (IS41C16256) and low-voltage industrial (IS41LV16256) variants. It specifies operating conditions for 5V and 3.3V supplies, provides truth tables for read/write operations, and lists absolute maximum ratings including temperature ranges from -40°C to +85°C.
| Memory Capacity | 262,144 x 16-bit (4-MBIT) |
|---|---|
| Package Types | 40-pin SOJ and TSOP (Type II) |
| Refresh Interval | 512 cycles/8 ms |
| Supply Voltage (IS41C16256) | 5V ± 10% |
| Operating Temperature (Commercial) | 0 to +70 °C |
| Operating Temperature (Extended/Industrial) | -40 to +85 °C |
| Min. EDO Page Mode Cycle Time (-35°C) | 22 ns |
The device has a capacity of 262,144 x 16-bit (4-MBIT).
A refresh interval of 512 cycles per 8 ms period is required.