This document describes the features of Integrated Silicon Solution, Inc. (ISSI)'s IS41LV16256B product. The product is a 262,144 x 16-bit high-performance CMOS dynamic random access memory with TTL compatible inputs and outputs, a refresh interval of 512 cycles/8 ms, support for refresh modes and JEDEC standard pinout, and single power supply. It is ideal for use in 16 and 32-bit wide data bus systems.
The document is a technical specification for the ISSI IS41LV16256B, a 256K x 16-bit Dynamic Random Access Memory (DRAM). It features an accelerated cycle access EDO Page Mode allowing up to 512 random accesses within a single row with a minimum access time of 10ns per 16-bit word. The device supports TTL compatible inputs and outputs, operates on a single 3.3V power supply, and is available in 40-pin SOJ and TSOP (Type II) packages. This manual is written in Chinese.
| Capacity | 256K x 16 (4-MBIT) |
|---|---|
| Access Time | Max. 10ns per 16-bit word |
| Refresh Interval | 512 cycles/8 ms |
| Power Supply Voltage | 3.3V ± 10% |
| Package Types | 40-pin SOJ and TSOP (Type II) |
| Operating Temperature | 0 to +70 °C |
The minimum EDO Page Mode Cycle Time (t PC) is 42.5 ns, and the Max. CAS Access Time (t CAC) is 115 ns.
Yes, it supports Byte Write and Byte Read operation via two CAS signals.