Altera Stratix EP1S25 Device Pin Information

This document describes a product called Bank Number VREF Bank Pin. The product has multiple pins for different functions, including configuration and optional functions.


Altera Stratix EP1S25 Device Pin Information - cover page
Brand
Altera
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
27
File format
PDF
File size
675 KB
Published
01 August, 2012
Updated
28 September, 2023
MD5 checksum
0F2319F2D4666CCDA743BC2F1405E5D1

About this manual

This document provides a detailed pin list for the Stratix™ EP1S25 device, version 3.6. It includes pin names, functions, optional functions, and configuration settings for various banks within the device.

The data is organized by bank and function, specifying parameters such as VREF, speed, and differential I/O (DIFFIO) configurations. It also lists specific pin assignments for clock inputs, PLLs, and general-purpose I/Os.

What's inside

  • Pin Name/Function
  • Optional Function(s)
  • Configuration
  • Bank VREF
  • DIFFIO
  • Clock Inputs
  • PLL Configuration

Frequently asked questions

What is the document version for the Stratix EP1S25 pin information?

The document is version 3.6.

What is the document number for the Stratix EP1S25 pin list?

The document number is PT-EP1S25-3.6.

When was the Stratix EP1S25 pin list copyrighted?

The document was copyrighted in 2006.

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