This document describes the I/O features of Altera's Cyclone V devices, including support for different types of I/O standards and requirements.
Chapter 5 of the Cyclone V Device Handbook provides details about the I/O elements (IOEs) used in Cyclone V devices, including supported I/O standards such as LVDS, SLVS, RSDS, HSTL, HSUL, SSTL and programmable features like output current strength, slew‑rate, bus‑hold and on‑chip termination.
The chapter also covers design considerations, including I/O bank restrictions, VCCPD and VCCIO voltage relationships, VREF pin rules, LVDS channel usage, PLL configurations, and modular I/O bank layouts for different Cyclone V density families.
| LVDS VCCPD voltage | 2.5 V |
|---|
Use a slow slew‑rate and series termination on the transmitter to limit overshoot and undershoot at the I/O pins.