This chapter describes the hardware features that support high-speed memory interfacing for each double data rate (DDR) memory standard in HardCopy® III devices. HardCopy III devices feature delay-locked loops (DLLs), phase-locked loops (PLLs), dynamic on-chip termination (OCT), read-and-write leveling, and deskew circuitry. This chapter contains the following sections:...
This document serves as a technical reference for the HardCopy III device family, specifically focusing on external memory interfaces. It describes hardware features that support high-speed memory interfacing for various double data rate (DDR) memory standards, including DDR3, DDR2, DDR SDRAM, QDRII+, QDRII SRAM, and RLDRAM II.
The handbook outlines the redesigned HardCopy III I/O structure designed to provide flexible and high-performance support for these external memory standards. It details specific pin utilization strategies, data paths involving DLLs and PLLs, and the configuration of read-and-write leveling circuitry required for different memory types.
| Supported Memory Standards | DDR3, DDR2, DDR SDRAM, QDRII+, QDRII SRAM, RLDRAM II |
|---|---|
| Interface Features | DLLs, PLLs, dynamic OCT, read-and-write leveling, deskew circuitry |
| DQ Group Widths | 4 to 36-bit |
| External Memory Support Location | All sides of the HardCopy III device |
HardCopy III devices are designed to support the same I/O standards and implementation guidelines as Stratix III devices.
No, PLL reconfiguration is not required because the AltMEMPHY megafunction has an auto calibration feature.
Differential DQS pin-pairs are denoted as DQS and DQSn pins.