Altera Cyclone FPGA PLL Usage Manual Chapter 6

About this manual

Cyclone FPGAs contain up to two PLLs per device that offer clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs. These features allow for system-level clock management and skew control without the need for external devices.

The document details how to enable Cyclone PLLs using the altpll megafunction in Quartus II software. It describes the internal components of the PLL block diagram, including the Phase Frequency Detector (PFD), Charge Pump, Loop Filter, and Voltage Controlled Oscillator (VCO).

What's inside

• Introduction
• Hardware Overview
• Cyclone PLL Blocks
• Software Overview
• PLL Input Signals
• Pins and Clock Network Connections
• PLL Output Signals
• Global Clock Network Destinations

Specifications

Frequently asked questions

How are Cyclone PLLs enabled in Quartus II software?

Cyclone PLLs are enabled by using the altpll megafunction.

What is the function of the pllena signal?

It acts as a combined enable and reset signal; driving it low disables outputs and loses lock, while driving it high starts the re-synchronization process.

Can inverted clocks drive the Cyclone PLL?

No, you must drive Cyclone PLLs by the dedicated clock input pins CLK[3..0].