Altera EPF6016A Device Pin-Outs Datasheet

About this manual

The document presents a comprehensive pin-out table for the EPF6016A field-programmable gate array (FPGA). It lists specific pins such as MSEL, nSTATUS, and DCLK alongside their corresponding pad numbers for 100-Pin TQFP, 100-Pin FineLine, 144-Pin TQFP, 208-Pin PQFP, and 256-Pin FineLine packages.

What's inside

• MSEL
• nSTATUS
• DCLK
• CONF_DONE
• INIT_DONE
• VCCINT
• VCCIO
• GND
• Notes
• Pin Compatibility

Frequently asked questions

What is the total number of user I/O pins for the EPF6016A in the 100-Pin TQFP package?

The 100-Pin TQFP package has a total of 81 user I/O pins.

Which pins must not be used as user I/O pins when migrating from an EPF6024AF256 device?

Pins A2, A7, A9, A10, A13, A14, B1, B3, B7, B9, B11, B16, C1, C2, C7, D2, D15, D16, E14, F2, G15, G16, H16, J1, J2, K3, L2, L16, M15, N3, N15, P11, P15, R1, R5, R6, R9, R11, R16, T1, T2, T4, T6, T10, T11, T12, and T14 must not be used.

Can a pin listed as a dedicated configuration or JTAG pin be used as a user I/O pin?

Yes, it can be used as a user I/O pin if it is not used for its chip-wide or configuration function.