Altera EP1K10 FPGA Device Pin-Outs Datasheet

About this manual

The document serves as a reference guide for the physical pin assignments of the EP1K10 Field-Programmable Gate Array (FPGA). It details the layout for four specific package configurations: 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, and 256-Pin FineLine BGA.

The text lists dedicated pins required for configuration and operation, such as MSEL, INIT_DONE, CE, ICBO, and various data lines (DATAT through DATA7). It also identifies specific power supply pins like VCCINT and hWOCIO, along with notes on their voltage requirements. The document clarifies which pins are available for user I/O versus those dedicated to internal functions.

What's inside

• 100-Pin TQFP
• 144-Pin TQFP
• 208-Pin PQFP
• 256-Pin FineLine BGA
• Configuration Pins
• Power Supply Pins
• User I/O Pins
• Dedicated Inputs

Specifications

Frequently asked questions

What are the supported package types for the EP1K10?

The device is available in 100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, and 256-Pin FineLine BGA packages.

What voltage should be used to power the ClockLock and ClockBoost circuitry if the PLL is not used?

The pin should be connected to VCCINT or GNDINT.

Under what condition does the LOCK pin go low?

The LOCK pin goes low if a periodic clock stops clocking.