This document introduces the interface and integration information of Altera Stratix V devices, including configuration schemes, instructions on how to execute the required configuration schemes, and all the necessary option pin settings
This document provides technical information regarding the configuration, design security, and remote system upgrade capabilities of Stratix V devices. It covers supported configuration schemes including Fast Passive Parallel (FPP), Active Serial (AS), Passive Serial (PS), and JTAG, along with necessary option pin settings.
The guide also describes the power-on reset (POR) circuit behavior, voltage requirements for configuration pins (VCCPGM and VCCPD), and the specific sequence required to successfully configure the device from power-up through initialization.
| Supported configuration voltages (VCCPGM) | 1.8, 2.5, and 3.0 V |
|---|---|
| VCCPD voltage requirement | 3.0 V or 2.5 V |
All monitored power supplies must ramp up from 0 V to the desired voltage level within the specified time, or nCONFIG must be held low until they are stable.
The maximum delay for a standard power-on reset is 300 ms.
The supported configuration voltages for the VCCPGM pin are 1.8, 2.5, and 3.0 V.