This document is a preliminary pin connection guidelines for Altera’s Arria® V Device Family
The Arria V Device Family Pin Connection Guidelines (PCG-01013-1.4) serve as a recommendation rather than a specification for connecting programmable logic devices. Users are advised to verify all designs against the specific device datasheet and Altera's standard warranty before implementation.
The document details connection guidelines for various pin types, including Clock and PLL pins (CLKOUTO, FBp, etc.), Dedicated Configuration/ITAG pins (MSEL, AS_DATAQ, nCSO), and Status pins (nSTATUS, nCE, nCONFIG, CONF_DONE, nCEO). It specifies how to tie unused pins to GND or VCCPGM using internal Quartus II options or external pull-up resistors.
No, the guidelines are preliminary and should only be used as a recommendation.
During JTAG programming, the status of the nCONFIG pin is ignored.