This document describes a novel method for an off-line power factor correction (PFC) - PWM combo controller. The controller improves power usage efficiency and reduces harmonic content in the line current.
This document is an application note for the Fairchild ML4824, a controller IC designed for off-line power factor correction (PFC) and pulse width modulation (PWM) cascade converters. It introduces a novel method using a leading/trailing edge modulation scheme to synchronize two cascaded power stages, thereby reducing output ripple voltage and simplifying loop compensation compared to traditional trailing edge modulation.
The application circuit is designed to accept an AC input voltage ranging from 80 to 264V.
The comparison was conducted with a 50pF capacitor, 220V AC input, 75W average power, 80kHz frequency, and 1.5mH inductance.
The evaluation showed that the 120Hz component of the output ripple voltage was reduced by 30%.