Silicon Storage Technology SST 28SF040 4 Megabit SuperFlash EEPROM Datasheet

This document describes the features and characteristics of SST 28SF040 5.0V-only 4 Megabit SuperFlash EEPROM, including 5V read and write operations, CMOS SuperFlash EEPROM technology, memory organization, sector erase capability, low power consumption, fast erase and programming operations, data protection features, and data interface compatibility.


Silicon Storage Technology SST 28SF040 4 Megabit SuperFlash EEPROM Datasheet - cover page
Brand
SST
Category
Memory
Document type
Datasheet
Language
English
Pages
24
File format
PDF
File size
1.1 MB
Published
09 July, 2012
Updated
29 September, 2023
Model
28SF040
MD5 checksum
67E68D5094337A9822E945D303F9C17F

About this manual

The SST 28SF040 is a 512K x 8 bit CMOS sector erase, byte program EEPROM manufactured using Silicon Storage Technology's proprietary SuperFlash technology. It operates with a single 5.0-volt power supply and is compatible with industry standard EPROM, flash EPROM, and EEPROM pinouts. The device is designed for applications requiring reprogrammable nonvolatile mass storage of program, configuration, or data memory.

What's inside

  • Features
  • Product Description
  • Device Operation
  • Sector_Erase Operation
  • Chip_Erase Operation
  • Byte_Program Operation
  • Read_ID operation
  • Data Protection
  • Write Operation Status Detection

Specifications

Memory Capacity4 Megabit (512K x 8)
Endurance100,000 Cycles (typical)
Data RetentionGreater than 100 years
Active Current15 mA (typical)
Standby Current5 uA (typical)
Byte Program Time35 us (typical)
Sector Erase Time2ms (typical)
Complete Memory Rewrite Time20 sec (typical)
Access Time120, 150, and 200 ns
Sector Size256 bytes per Sector

Frequently asked questions

What is the power supply requirement for the SST 28SF040?

The device erases and programs with a 5.0-volt only power supply.

How can the end of a write cycle be detected?

The end of a write cycle can be detected by monitoring the Data# Polling bit, the Toggle bit, or by two successive reads of the same data.

What is the maximum time for a Chip Erase operation?

The Chip Erase operation will terminate after a maximum of 20 ms.

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