National Semiconductor DS90C032B Quad CMOS Differential Line Receiver Datasheet

The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.


National Semiconductor DS90C032B Quad CMOS Differential Line Receiver Datasheet - cover page
Brand
National Semiconductor
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
9
File format
PDF
File size
163 KB
Published
04 July, 2012
Updated
30 September, 2023
MD5 checksum
5530FB6A775C25CEE35EA44185A25800

About this manual

The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates, supporting speeds in excess of 155.5 Mbps using Low Voltage Differential Signaling (LVDS) technology. It accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels.

What's inside

  • General Description
  • Features
  • Absolute Maximum Ratings
  • Electrical Characteristics
  • Switching Characteristics
  • Parameter Measurement Information
  • Typical Application
  • Applications Information
  • Receiver Fail-Safe

Specifications

Data Rate>155.5 Mbps (77.7 MHz)
Input Signal Level350 mV differential
Operating TemperatureIndustrial range
Maximum Propagation Delay6.0 ns
Maximum Differential Skew600 ps

Frequently asked questions

What is the maximum data rate supported?

The device supports data rates in excess of 155.5 Mbps (77.7 MHz).

What input signal level does the receiver accept?

It accepts low voltage (350 mV) differential input signals.

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