This document introduces the PSoC™ family of products, which includes configurable blocks of analog and digital logic as well as programmable interconnects. These features allow users to create customized peripheral configurations that meet the requirements of each individual application.
This data sheet provides an overview of the Cypress PSoC™ Mixed‑Signal Array family, describing the Harvard‑architecture processor, programmable clocking, and the extensive on‑chip resources such as flash, SRAM, EEPROM, analog and digital blocks. It explains the system architecture, including the global digital and analog interconnects, and the configurable PSoC blocks that enable custom peripheral creation.
The document also outlines development resources, including the PSoC Designer IDE, development kits, tele‑training, technical support, and hardware tools like the In‑Circuit Emulator. It lists the device’s key specifications, peripheral options, and how to obtain ordering, packaging, and electrical data from Cypress’s website.
| Operating Voltage | 3.0 V to 5.25 V |
|---|---|
| Flash Program Storage | 32 KB |
| SRAM Data Storage | 2 KB |
| EEPROM Emulation | up to 2 KB |
| Industrial Temperature Range | -40 °C to +85 °C |
| Digital PSoC Blocks | up to 16 |
| Analog PSoC Blocks | up to 12 |
| UARTs | up to 4 Full‑Duplex UARTs |
| ADC Resolution | up to 14‑bit |
| DAC Resolution | up to 9‑bit |
| Internal Main Oscillator (IMO) | 24 MHz ±2.5 % over temperature and voltage |
The recommended environment is the PSoC Designer Integrated Development Environment (IDE).
The family provides up to 16 digital PSoC blocks and up to 12 analog PSoC blocks.