The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
The Philips PCK2509SL is a 50‑150 MHz 1:9 SDRAM clock driver that uses an integrated PLL to distribute a low‑skew, low‑jitter clock to nine outputs. It operates from a 3.3 V supply and supports both 2.5 V and 3.3 V input levels.
The document provides detailed specifications, pin descriptions, functional block diagram, absolute maximum ratings, recommended operating conditions, and characteristic curves for design engineers.
| Supply voltage (Vcc) | 3.3 V |
|---|---|
| Pin‑to‑pin skew | < 200 ps |
| Peak‑to‑peak jitter | +80 ps |
| Cycle‑to‑cycle jitter | 65 ps |
| Stabilization time | 1 ms |
| Operating temperature range | 0 °C – +70 °C |
| Package type | 24‑Pin Plastic TSSOP (SOT355‑1) |
It requires a 3.3 V supply (Vcc).
It provides nine low‑skew clock copies: five in bank 1 and four in bank 2.
The pin‑to‑pin skew is less than 200 ps.