Update: 28 September, 2023
The SY10/100E451 is a 6-bit register with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. A logic HIGH on the Master Reset (MR) input resets all outputs to a logic LOW. The VBB output is provided for use as a reference voltage for single-ended reception of ECL signals to that device only. Features include a minimum toggle frequency of 1100MHz, extended -4.2V to -5.5V VEE range, internal 75KΩ input pulldown resistors, etc.
File format: PDF
Size: -
MD5 Checksum: 142C47522967CCE38ED6F4DB1AD84DB2
Publication date: 10 May, 2012
Downloads: -
PDF Link: Micrel SY10E451 SY100E451 Manual PDF