The SY10/100E451 is a 6-bit register with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. A logic HIGH on the Master Reset (MR) input resets all outputs to a logic LOW. The VBB output is provided for use as a reference voltage for single-ended reception of ECL signals to that device only. Features include a minimum toggle frequency of 1100MHz, extended -4.2V to -5.5V VEE range, internal 75KΩ input pulldown resistors, etc.
The SY10E451 and SY100E451 are six‑bit register devices with differential data and clock inputs and single‑ended outputs, intended for high‑performance ECL systems. They are triggered on the rising edge of the clock and include a VBB reference output for single‑ended reception.
Key features include a minimum 1100 MHz toggle frequency, differential inputs, a VBB output decoupled with a 0.01 µF capacitor, and compatibility with standard 10 kΩ and 100 kΩ ECL levels. The devices are supplied in a 28‑lead PLCC (J28‑1) package and are available with several ordering codes.
| Toggle Frequency (fMAX) | 1100‑1400 MHz |
|---|---|
| VBB Output Reference Voltage | -1.35 V (typical) |
| Input HIGH Current (IIH) | 150 µA (typical) |
| Propagation Delay tPLH | 650 ps (typical) |
| Package | 28‑lead PLCC (J28‑1) |
A 0.01 µF capacitor should be used to decouple VBB to VCC.
Both devices are supplied in a 28‑lead PLCC (J28‑1) package.
The characteristics are given for TA = 0 °C, CT A = 25 °C, and CT A = 85 °C.