The SY100S834/L is a low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal clock of maximum frequency of 100MHz.
The SY100S834/SY100S834L ClockWorks chip family offers low‑skew clock generation with selectable divide ratios (+1, +2, +4, +8). It supports both differential and single‑ended ECL/PECL inputs, and includes a VBB output that can be used as a sinusoidal source or reference for single‑ended operation. The device includes synchronous enable (EN) and master reset (MR) inputs to ensure glitch‑free operation.
The datasheet lists detailed DC and AC electrical characteristics, including power‑supply current, output reference voltage, input current limits, propagation delays, setup/hold times, and within‑device skew. Package information (16‑lead SOIC) and ordering codes for commercial and industrial variants are also provided.
| Input HIGH Current (MH) | 150 mA |
|---|---|
| Setup Time (EN) | 400 ps |
| Hold Time (EN) | 200 ps |
| Minimum Input Swing (VPP) | 250 mV |
| Package | 16‑lead SOIC |
The device can be powered from either a 3.3 V or a 5 V supply.
EN is synchronous, so the internal dividers are enabled or disabled only when the internal clock is already low, avoiding runt pulses.
The VBB pin can source or sink up to 0.5 mA of current.