The SY10/100E452 is a 5-bit differential register with differential data inputs and outputs and a clock. It features an inverted master reset input and asynchronous master reset, making it suitable for high-frequency applications.
The SY10E452 and SY100E452 are 5‑bit differential registers with differential data and clock inputs. They operate on a positive clock edge and include an asynchronous master reset that forces all Q outputs low. The devices are supplied in a 28‑pin PLCC package and are suited for high‑frequency applications requiring a registered data path.
The datasheet details DC and AC electrical characteristics, including a VEE range of –4.2 V to –5.5 V, a minimum toggle frequency of 1100 MHz, propagation delays, and input swing requirements. Ordering codes for commercial and industrial variants are also listed.
| VEE voltage range | -4.2 V to -5.5 V |
|---|---|
| Minimum toggle frequency | 1100 MHz |
| Typical propagation delay (tPHL, differential) | 600 ps |
| Minimum input swing (AC) | 150 mV |
The devices operate with a VEE range from –4.2 V to –5.5 V.
The minimum toggle frequency is 1100 MHz.
Both devices are available in a 28‑pin PLCC package.
A high on the Master Reset asynchronously resets all registers, causing the Q outputs to go LOW.