This manual describes the hardware features and usage of the SH7040 series chips (CPU core is SH-2).
The SH7040 series (SH7040, SH7041, SH7042, SH7043, SH7044, SH7055) are 32‑bit single‑chip RISC microprocessors that integrate a Renesas‑designed SH‑2 CPU core with on‑chip peripherals such as ROM, RAM, timers, serial interfaces, A/D converter, interrupt controller and I/O ports. The CPU executes most instructions in a single clock cycle and features a 32‑bit internal bus and a 1‑kbyte on‑chip cache for high performance.
This hardware manual provides detailed information on the series' hardware architecture, register definitions, DMA controller, board‑design guidelines and usage notes. It also lists revisions, specifications and safety cautions for designers developing systems with these microprocessors.
| CPU core | SH-2 |
|---|---|
| Internal bus width | 32‑bit |
| On‑chip cache size | 1 kbyte |
| On‑chip ROM types | mask ROM, PROM, flash memory |
| Memory capacity | large‑capacity ROM and RAM |
| Peripheral interfaces | timers, serial communication interface (SCD), A/D converter, interrupt controller, I/O ports |
Designers should keep safety first by using non‑flammable materials, adding auxiliary circuits, and preventing malfunctions or mishaps.
Most instructions can be executed in one clock cycle.