Update: 30 September, 2023
The MAX 7000 Programmable Logic Device Family is a family of high-performance EEPROM-based programmable logic devices (PLDs) based on the second-generation MAX architecture. The family includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices. MAX 7000S devices include built-in JTAG boundary-scan test (BST) circuitry in devices with 128 or more macrocells. The family has logic densities ranging from 600 to 5,000 usable gates and has 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect).
File format: PDF
Size: -
MD5 Checksum: B6C2C51CC2DDC03BE4116632B872F3C0
Publication date: 08 May, 2012
Downloads: -
PDF Link: ALTERA MAX 7000 handbook(3) PDF