The MAX 7000 Programmable Logic Device Family is a family of high-performance EEPROM-based programmable logic devices (PLDs) based on the second-generation MAX architecture. The family includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices. MAX 7000S devices include built-in JTAG boundary-scan test (BST) circuitry in devices with 128 or more macrocells. The family has logic densities ranging from 600 to 5,000 usable gates and has 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect).
The MAX 7000 programmable logic device family offers EEPROM‑based PLDs with densities from 600 to 5,000 usable gates, supporting both 3.3‑V and 5.0‑V operation. Devices include a range of package types (PLCC, PGA, PQFP, RQFP, TQFP) and provide in‑system programmability via JTAG and IEEE‑standard interfaces.
Key features include up to 5‑ns pin‑to‑pin delays, 175.4 MHz counter frequencies, open‑drain outputs, multi‑voltage I/O, and optional power‑saving modes. The family is supported by Altera development tools for Windows, Sun SPARC, and HP workstations.
| Usable gates | 600 to 5,000 |
|---|---|
| Macrocells | 32 to 256 |
| Pin‑to‑pin delay | 5 ns |
| Maximum counter frequency | 175.4 MHz |
| Operating voltage | 3.3 V or 5.0 V |
The family is offered in PLCC, PGA, PQFP, RQFP, and TQFP packages, ranging from 44 to 208 pins.
MAX 7000 devices can operate at either 3.3 V or 5.0 V, allowing mixed‑voltage system designs.