Altera Stratix V, Arria V, Cyclone V, HardCopy Product Catalog


Altera Stratix V, Arria V, Cyclone V, HardCopy Product Catalog - cover page
Brand
Altera
Category
Other Electronics
Document type
Product Leaflet
Language
English
Pages
92
File format
PDF
File size
1.7 MB
Published
01 August, 2012
Updated
29 September, 2023
MD5 checksum
EBA00D10EEF010927E98D50E09E129F4

About this manual

This document serves as a comprehensive product catalog for Altera's logic device portfolio, including FPGAs, SoC FPGAs, ASICs, and CPLDs. It highlights the company's flagship Stratix series for high density and performance, the Arria series for high-performance computation, and the Cyclone series for cost-sensitive applications. The catalog also covers SoC FPGAs which integrate ARM-based hard processor systems.

What's inside

  • Stratix V GT FPGA Features
  • Stratix V GX FPGA Features
  • HardCopy series device support
  • Arria FPGA Series
  • Cyclone FPGA Series
  • MAX CPLD Series
  • Quartus II Software
  • Embedded Processing
  • Intellectual Property
  • Development Kits

Specifications

Maximum LEs (Stratix V GT 5SGTC7)622 K
Maximum M20K memory blocks (Stratix V GT 5SGTC7)2,560
Maximum Variable-precision DSP blocks (Stratix V GT)256
Supported I/O voltage levels1.2, 1.5, 1.8, 2.5, 3.3 V
Supported I/O standardsLVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL
Embedded DPA circuitry3
Global clock networks16
Regional clock networks92
Design security3

Frequently asked questions

What FPGA series does Altera offer?

Altera offers three classes of FPGAs: Stratix for highest density and performance, Arria for high-performance computation, and Cyclone for lowest power and cost.

What is a SoC FPGA?

SoC FPGA devices consolidate two discrete devices into one, integrating an ARM-based hard processor system (HPS) with FPGA fabric using a high-bandwidth interconnect backbone.

What is the purpose of the HardCopy series?

The HardCopy series is used for volume production after prototyping designs with Stratix series FPGAs, offering the shortest time to market and lowest overall ASIC development costs.

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