The MAX 7000 series is a high-performance, EEPROM-based programmable logic device (PLD) family based on the second-generation MAX architecture, featuring 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.
The MAX 7000 family is a line of EEPROM‑based programmable logic devices offering 600 to 5,000 usable gates, in‑system programmability, and fast pin‑to‑pin delays as low as 5 ns. Devices support 3.3‑V or 5.0‑V operation and are available in a variety of packages such as PLCC, PGA, PQFP, RQFP and TQFP.
The data sheet provides detailed tables of device features, speed grades, pin counts, and programming hardware (BitBlaster, ByteBlaster, MasterBlaster). It also describes the architecture, including macrocell structure, logic array blocks, and optional power‑saving and security features.
| Usable gates | 600 to 5,000 |
|---|---|
| Maximum pin‑to‑pin delay | 5 ns |
| Maximum counter frequency | 175.4 MHz |
| Operating voltage | 3.3 V or 5.0 V |
| Number of macrocells | 32 to 256 |
Speed grades include -10P, -10, -12P, -15T, and -20, as listed in the data sheet.
A MAX 7000 device can contain between 32 and 256 macrocells.
Yes, a programmable power‑saving mode can reduce power consumption by over 50 % per macrocell.