This is the Altera Cyclone FPGA family data sheet, which introduces the characteristics of the products in the series.
This datasheet provides designers with detailed specifications for the Altera Cyclone FPGA family, covering device architecture, configuration, testing, DC and switching characteristics, and reference and ordering information. It includes feature tables, package options, and resource counts for each device variant.
The document also describes the internal logic array blocks, embedded memory, I/O standards, PLL resources, and global clock network, along with migration guidance and pin‑out details. Ordering codes and package types are listed for easy selection of the appropriate device.
| Logic Elements (LEs) | 2,910 to 20,060 |
|---|---|
| Embedded RAM | Up to 294,912 bits (36,864 bytes) |
| PLL count per device | Up to 2 |
| Global clock lines | 8 |
| Maximum I/O pins | 301 (for EP1C4/EP1C20) |
A Cyclone device can contain up to 20,060 logic elements.
Each Cyclone device provides up to two PLLs.
The family supports up to 294,912 RAM bits (36,864 bytes).
Cyclone devices support LVDS, LVTTL, LVCMOS, SSTL‑2, SSTL‑3, and PCI I/O standards.