Altera Configuration Handbook Volume 2

About this manual

This handbook covers Altera's FPGA configuration devices, including enhanced, serial, and SRAM‑based LUT devices. It explains device features, pin descriptions, power sequencing, and ordering information.

The document also offers software implementation guidance, configuration file format details, advanced configuration schemes, board layout tips, and extensive debugging suggestions for both flash‑memory and JTAG configurations.

What's inside

• About this Handbook
• FPGA Configuration Devices
• Enhanced Configuration Devices
• Serial Configuration Devices
• Configuration Devices for SRAM‑Based LUT Devices
• Device Configuration Options
• Configuration File Formats
• Advanced Configuration Schemes
• Board Layout Tips & Debugging Techniques
• Debugging Configuration Problems

Frequently asked questions

How can I verify that a configuration device has been programmed successfully?

Use the Quartus II programmer to perform a Verify on the configuration device.

What does it mean when the FPGA pulls nSTATUS low during configuration?

It indicates that the FPGA has detected a CRC error in the configuration data.

What should be connected to the nCONFIG pin during JTAG configuration?

The nCONFIG pin must be tied to VCC or driven high.

What is the recommended connection for the TRST pin in JTAG configuration?

TRST (if available) should be connected to VCC.