APEX 20K is Altera's first programmable logic device (PLD) that incorporates system-on-a-programmable-chip (SOPC) integration, MultiCoreTM architecture, look-up table (LUT) logic, product-term logic, and embedded memory. It features high density, high performance, and flexibility. APEX 20K can be used to build various electronic systems, such as ASICs, FPGAs, CPLDs, SoCs, DSPs, etc.
This document describes the Altera APEX 20K Programmable Logic Device (PLD) Family, which is the industry's first PLD to incorporate system-on-a-programmable-chip (SOPC) integration. The family utilizes a MultiCore architecture that combines look-up table (LUT) logic for register-intensive functions with product-term logic for combinatorial-intensive tasks.
| Up to logic elements (LEs) | 51,840 |
|---|---|
| Up to RAM bits | 442,368 |
| Internal supply voltage (Vccint) | 1.8 V or 2.5 V |
| MultiVolt I/O interface voltages | 1.8 V, 2.5 V, 3.3 V, 5.0 V |
The maximum number of logic elements (LEs) that can be used without reducing available RAM bits is up to 51,840.
The devices support an internal supply voltage of 1.8 V and a MultiVolt I/O interface that supports 1.8-V, 2.5-V, 3.3-V, and 5.0-V levels.
The bidirectional I/O performance (tCg + tCO) can reach up to 250 MHz.