Altera EP220 / EP224 Classic EPLDs are high-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells. Combinatorial speeds as low as 7.5 ns, counter frequencies up to 100 MHz, pipelined data rates up to 115 MHz, maximum 5.5-ns Clock-to-output time, minimum 4.5-ns setup time.
The document is a data sheet for the Altera EP220 and EP224 Classic EPLDs, released in May 1995. These devices are described as high-performance, low-power Erasable Programmable Logic Devices (EPLDs) with up to 8 macrocells each. They offer combinatorial speeds as low as 7.5 ns and counter frequencies of up to 100 MHz.
| Combinatorial speed | as low as 7.5 ns |
|---|---|
| Counter frequencies | up to 100 MHz |
| Pipelined data rates | up to 115 MHz |
| Maximum Clock-to-output time | 5.5-ns |
| Minimum setup time | 4.5-ns |
The devices support counter frequencies of up to 100 MHz.
Yes, macrocells are independently programmable for both registered and combinatorial logic.
It provides total protection of proprietary designs by making programmed data invisible when turned on.