APEX 20K is Altera's first programmable logic device (PLD) that incorporates system-on-a-programmable-chip (SOPC) integration. It uses MultiCoreTM architecture, which integrates lookup table logic, product term logic, and embedded memory. Lookup table logic is used for register-intensive functions, embedded system block is used to implement memory functions, including first-in first-out buffers, dual-port RAM, and content-addressable memory. Embedded product term logic is used for combinatorial-intensive functions.
This document is a data sheet for the Altera APEX 20K Programmable Logic Device Family. It introduces the MultiCore™ architecture which integrates look-up table (LUT) logic and embedded system block (ESB) memory functions into a single chip. The family includes devices ranging from 30,000 to 1.5 million typical gates.
| Architecture | MultiCore™ architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory |
|---|---|
| Logic Elements (LEs) | Up to 51,840 |
| RAM bits | Up to 442,368 |
| Macrocells | Up to 3,456 product-term-based macrocells |
| Supply Voltage | 1.8V and 2.5V (Internal) |
| I/O Interface Voltages | 1.8V, 2.5V, 3.3V, and 5.0V |
| Clock Management | Up to four phase-locked loops (PLLs) |
| Global Clock Signals | Up to eight |
The family supports up to 51,840 logic elements.
The devices support a bidirectional I/O performance up to 250 MHz.
The architecture provides support for up to eight global clock signals.