The MACH 5 CPLD Family Fifth Generation MACH Architecture is a logic integrated circuit product with high logic density and input/output interfaces to support various application needs. It also features high-performance characteristics, flexible architecture design for convenient logic design and system integration. It supports advanced capabilities such as boundary scan testing and programmable security bit. It is based on advanced E2CMOS process, providing high-performance and cost-effective solutions.
The MACH 5 CPLD family offers high logic densities (128 to 512 macrocells) and a wide range of I/O options (68 to 256 pins) across multiple package types. It supports both 5‑V (M5‑xxx) and 3.3‑V (M5LV‑xxx) operation, with programmable power and speed settings, boundary‑scan testability, and in‑system programming via IEEE 1149.1.
Performance includes up to 182 MHz operation, tPD as low as 5.5 ns (commercial) or 7.5 ns (industrial), and typical static power ranging from 35 mA to 100 mA depending on density. The family is PCI‑compliant for several speed grades and provides extensive clocking and reset options for flexible design.
| Macrocell density | 128 to 512 |
|---|---|
| I/O pins | 68 to 256 |
| Propagation delay (tPD) commercial | 5.5 ns |
| Maximum operating frequency | 182 MHz |
| Supply voltage options | 5‑V and 3.3‑V |
| Typical static power | 35 mA – 100 mA |
| Package types | 100‑pin TQFP, 144‑pin TQFP, 160‑pin PQFP, 208‑pin PQFP, 240‑pin PQFP, 256‑ball BGA, 352‑ball BGA |
MACH 5 devices are offered in 5‑V (M5‑xxx) and 3.3‑V (M5LV‑xxx) versions.
Yes, MACH 5 devices include IEEE 1149.1 boundary‑scan registers and are compliant with the standard.
The family can operate up to 182 MHz.
The highest‑density device provides 512 macrocells.