The CY7C109B / CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits, with features such as high speed, low power consumption, low CMOS standby power, 2.0V data retention, automatic power-down and TTL-compatible inputs and outputs.
The CY7C109B and CY7C1009B are high‑performance CMOS static RAM devices organized as 128K × 8 bits. They offer low active power, low standby power, and TTL‑compatible I/O with easy memory expansion via multiple chip‑enable and output‑enable options.
The document provides detailed electrical specifications, switching characteristics, data‑retention behavior, and package information for both parts, including SOJ and TSOP options. Timing diagrams and truth tables illustrate read and write cycles for designers.
| Memory size | 128K × 8 bits |
|---|---|
| Maximum access time | 12 ns |
| Low active power | 495 mW (max.) |
| Low CMOS standby power | 55 mW (max.) |
| Data retention voltage | 2.0 V |
| Supply voltage range | -0.5 V to +7.0 V |
| Package (CY7C109B) | 400‑mil‑wide SOJ, 32‑pin TSOP |
| Package (CY7C1009B) | 300‑mil‑wide SOJ |
The CY7C109B has a maximum access time of 12 ns for the fastest speed grade.
In active mode the device draws up to 495 mW (max. at 12 ns access time).
The CY7C109B is offered in a 400‑mil‑wide SOJ and a 32‑pin TSOP, while the CY7C1009B is available in a 300‑mil‑wide SOJ.
Both parts retain data down to a minimum of 2.0 V.