This document describes the features and characteristics of Cypress Semiconductor Corporation's CPLD family Delta39K ISR. The series offers high density, embedded memory, high-speed operation, and support for multiple input/output standards.
The Delta39K family offers high‑density CPLDs with 30 K to 200 K usable gates, up to 3 428 I/O pins and embedded SRAM ranging from 80 K to 480 K bits. Devices support multiple I/O voltage standards (1.5 V‑3.3 V) and provide a 233 MHz in‑system operation speed, while standby current can be as low as 5 mA.
The architecture is based on Logic Block Clusters (LBC) connected by horizontal and vertical routing channels, with programmable interconnect matrix (PIM) and optional channel and cluster memory blocks. The family includes JTAG‑compliant ISR programming, boundary‑scan, and features such as user‑programmable bus‑hold, slew‑rate control, and AnyVolt I/O voltage flexibility.
| Usable gates | 30 K to 200 K |
|---|---|
| Macrocells | 512 to 3072 |
| Embedded SRAM | 80 K to 480 K bits |
| Channel memory | 16 K to 96 K bits (dual‑port) |
| Maximum operating frequency | 233 MHz |
| Standby current | as low as 5 mA |
| I/O voltage options | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
Delta39K devices provide between 30 K and 200 K usable gates.
The family supports 1.5 V, 1.8 V, 2.5 V and 3.3 V I/O voltage levels.
They can operate at up to 233 MHz in‑system.
Standby current can be as low as 5 mA.