Delta39K™ ISR™ CPLD Family features high density, high speed, low power, simple timing model, flexible clocking, multiple I/O standards, compatibility etc.
This manual describes the Delta39K ISR CPLD family, a high‑density, low‑power programmable logic solution from Cypress. It outlines key features such as up to 200 K usable gates, embedded SRAM, multiple voltage I/O options, and in‑system reprogrammability via JTAG.
The document details the device architecture, including Logic Block Clusters, macrocell structure, embedded channel and cluster memory, I/O bank organization, and timing specifications. It also includes tables of device variants, package options, and electrical characteristics.
| Usable gates | 30K to 200K |
|---|---|
| Macrocells | 512 to 3072 |
| Maximum I/O pins | 136 to 428 |
| Embedded SRAM | 80K to 480K bits |
| Channel memory | 16K to 96K bits |
| In‑system operation speed | 233 MHz |
| Standby current | as low as 5 mA |
Depending on the device variant, the family offers between 136 and 428 maximum I/O pins.
Yes, they feature In‑System Reprogrammable (ISR) functionality via a JTAG‑compliant serial interface.