The TMS320LF240xA/LC240xA DSP controllers provide 40-MIPS performance with a 25-ns instruction cycle time (40 MHz). They feature a low-power 3.3-V design based on the TMS320C2xx DSP CPU core. These devices are available in LF and LC packages. The LF package provides erasable flash, while the LC package provides programmable ROM. All devices provide a programmable code-security feature.
The TMS320LF2407A is a 40‑MIPS, 25‑ns instruction‑cycle digital signal processor built on a static CMOS process. It offers up to 32 K words of flash or ROM, 544 words of dual‑access RAM, and a range of motor‑control peripherals such as PWM channels, event managers, and a 10‑bit ADC.
The device includes serial interfaces (SCI, SPI, CAN 2.0B), up to 40 programmable GPIO pins, an external memory interface of up to 192 K words, and power‑down modes for each peripheral. It is supplied at 3.3 V and is supported by Texas Instruments' Code Composer Studio development tools.
| Instruction Cycle Time | 25 ns |
|---|---|
| Performance | 40 MIPS |
| Supply Voltage | 3.3 V |
| On‑Chip Flash Memory | Up to 32 K words × 16‑bit |
| Dual‑Access RAM | 544 words |
| ADC Resolution | 10‑bit |
| ADC Minimum Conversion Time | 500 ns |
| GPIO Pins | Up to 40 programmable pins |
| External Memory Interface Capacity | 192 K words × 16‑bit total |
| CAN Module | CAN 2.0B compliant |
The instruction cycle time is 25 ns.
It delivers 40 MIPS at 40 MHz.
The device operates from a 3.3 V supply.
Yes, it includes a CAN 2.0B module.