This document is about the production data of TMS320C1x digital signal processors. This series of products has high performance, miniaturization, low power consumption and other characteristics.
The TMS320C1x family is a series of 16‑bit digital signal processors that are object‑code compatible with the original TMS32010. They combine a high‑speed controller core with an array‑processor style architecture, delivering up to 8.77 MIPS performance. The family includes a range of devices (C10, C14, C15, C16, C17, and low‑power variants) with various memory sizes, I/O configurations, and package options.
The datasheet provides a quick reference table of device parameters, detailed architecture descriptions, instruction set summaries, and mechanical package drawings. It also covers peripheral features such as dual‑channel serial ports, companding hardware, coprocessor interfaces, and interrupt handling.
| On‑chip Data RAM | 144 or 256 words |
|---|---|
| On‑chip Program ROM | 1.5K‑ to 8K‑Word |
| On‑chip Program EPROM | 4K‑Word |
| Maximum Performance | Up to 8.77 MIPS |
| Operating Temperature | 0 °C to 70 °C |
| Package Types | DIP, PLCC, Quad Flatpack, CER‑QUAD |
| ALU/Accumulator Width | 32‑bit |
| Multiplier | 16 × 16‑bit with 32‑bit product |
| I/O Channels | Eight parallel I/O channels |
| Serial Port | Dual‑channel full‑duplex |
The TMS320C1x devices can achieve up to 8.77 MIPS.
They are offered in DIP, PLCC, Quad Flatpack, and CER‑QUAD packages.
Depending on the model, they provide either 144 or 256 words of on‑chip data RAM.
Device versions are available with cycle times of 160 ns, 200 ns, and 280 ns.