TMS320P25 is a member of the TMS320 family of VLSI digital signal processors and peripherals. It supports a wide range of digital signal processing applications, such as telecommunications, modems, image processing, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, and other computation intensive applications.
The TMS320P25 is a 40 MHz digital signal processor with a 100 ns instruction cycle, 4 K‑word on‑chip EPROM, 544 words of on‑chip data RAM and 128 K‑words of external data/program space. It features a 32‑bit ALU/accumulator, a 16 × 16‑bit multiplier, 16 parallel I/O ports, a serial port for codec interfacing, and a single 5‑V supply.
The document describes the modified Harvard architecture, memory map configurations, external interface signals, interrupt handling, multiprocessing options, and available packaging (68‑lead J‑lead chip carrier and 80‑lead QFP). An addendum lists obsolete package codes and regulatory information.
| Instruction Cycle Time | 100 ns (40 MHz) |
|---|---|
| On‑Chip Program EPROM | 4 K words |
| On‑Chip Data RAM | 544 words (16‑bit) |
| External Data/Program Space | 128 K words |
| Parallel I/O Ports | 16 |
| ALU/Accumulator Width | 32‑bit |
| Multiplier | 16 × 16‑bit, 32‑bit product |
| Supply Voltage | Single 5‑V |
| Packaging – FN | 68‑lead plastic J‑leaded chip carrier |
| Packaging – PH | 80‑lead plastic quad flatpack |
The instruction cycle time is 100 ns, corresponding to a 40 MHz clock.
It provides 16 parallel I/O ports.
The device includes 4 K words of EPROM, 544 words of data RAM, and up to 128 K words of external data/program space.
Two packages are listed: a 68‑lead plastic J‑lead chip carrier (FN) and an 80‑lead plastic quad flatpack (PH).