The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM that is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.
The X28HC256 is a second‑generation high‑performance 5 V CMOS 32 k × 8 EEPROM offering 70 ns access time, 1 M write‑cycle endurance and 100‑year data retention. It supports byte and 128‑byte page write operations, with a typical full‑memory rewrite time of under 0.8 s, and includes both DATA polling and Toggle‑Bit methods for write‑completion detection.
The document lists ordering information for multiple package types (CERDIP, PDIP, SO, PLCC, FLATPACK), provides detailed pinout diagrams, describes read/write timing, hardware and software data‑protection features, and includes mechanical dimensions for the Small Outline and Dual‑In‑Line packages.
| Access time | 70 ns |
|---|---|
| Supply voltage | 5 V single supply |
| Active current | 60 mA |
| Standby current | 500 nA |
| Endurance | 1 000 000 write cycles per byte |
| Data retention | 100 years |
A full page write typically completes in less than 0.8 seconds.
The device is rated for a minimum of 1 000 000 write cycles per byte.