Intersil HSP50210 Digital Costas Loop Datasheet

This document introduces the Intersil HSP50210 Digital Costas Loop, which can be used to demodulate BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM waveforms.


Intersil HSP50210 Digital Costas Loop Datasheet - cover page
Brand
Intersil
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
51
File format
PDF
File size
682 KB
Published
28 March, 2012
Updated
01 October, 2023
MD5 checksum
B3148A7248AD1639FF5EFDFA1FF28F9B

About this manual

The HSP50210 Digital Costas Loop (DCL) is a mixed‑signal IC that performs baseband processing for demodulating BPSK, QPSK, 8‑PSK, OQPSK, FSK, AM and FM waveforms. It includes a complex multiplier, selectable matched filters, AGC, carrier and symbol tracking loops, and a soft‑decision slicer, and is intended to be used together with the HSP50110 Digital Quadrature Tuner.

The document provides a functional description, pinout diagram, pin descriptions, ordering information, and timing diagrams. Key specifications such as clock rate, package type, temperature range and RoHS compliance are listed, along with register maps and configuration details for the internal loops and filters.

What's inside

  • Features
  • Pinout
  • Pin Description
  • Functional Description
  • Block Diagram
  • NCO/Mixer
  • Matched Filtering
  • Timing Diagrams
  • Ordering Information

Specifications

Clock rateUp to 52 MHz
Package84‑lead PLCC
RoHS compliancePb‑free version available, RoHS compliant
Interface8‑bit microprocessor control – status interface

Frequently asked questions

What is the maximum clock rate of the HSP50210?

The device supports clock rates up to 52 MHz.

What package does the HSP50210 use?

It is supplied in an 84‑lead PLCC package.

Is a Pb‑free version of the HSP50210 available?

Yes, a Pb‑free version is offered and is RoHS compliant.

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