This is the technical manual of HSP50110 Digital Quadrature Tuner. The tuner provides many of the functions required for digital demodulation, including carrier LO generation and mixing, baseband sampling, programmable bandwidth filtering, baseband AGC, and IF AGC error detection. Serial control inputs are provided which can be used to interface with external symbol and carrier tracking loops. These elements make the DQT ideal for demodulator applications with multiple operational modes or data rates. The DQT may be used with HSP50210 Digital Costas Loop to function as a demodulator for BPSK, QPSK, 8-PSK OQPSK, FSK, FM, and AM signals. The DQT processes a real or complex input digitized at rates up to 52 MSPS. The channel of interest is shifted to DC by a complex multiplication with the internal LO. The quadrature LO is generated by a numerically controlled oscillator (NCO) with a tuning resolution of 0.012Hz at a 52MHz sample rate. The output of the complex multiplier is gain corrected and fed into identical low pass FIR filters. Each filter is comprised of a decimating low pass filter followed by an optional compensation filter. The decimating low pass filter is a 3 stage Cascaded-Integrator-Comb (CIC) filter. The CIC filter can be configured as an integrate and dump filter or a third order CIC filter with a (sin(X)/X)3 response. Compensation filters are provided to flatten the (sin(X)/X)N response of the CIC. If none of the filtering options are desired, then the input is directly fed into the FIR filter.
The Digital Quadrature Tuner (DQT) processes real or complex inputs up to 52 MSPS, shifting the channel of interest to DC with a numerically‑controlled oscillator and low‑pass FIR filtering. It includes an internal AGC loop, input level detector and programmable decimation for flexible demodulation applications.
Key features include parallel or serial output formats, a bidirectional 8‑bit microprocessor interface, selectable low‑pass filter configurations (CIC, integrate‑and‑dump, bypass), and a compact 84‑lead PLCC package. Pinout and control signals are detailed for integration with external symbol‑tracking loops and Costas loops.
| Maximum Input Sample Rate | 52 MSPS |
|---|---|
| Output Data Formats | Parallel or Serial |
| Input Resolution | 10‑Bit Real or Complex |
| Microprocessor Interface | Bidirectional 8‑Bit |
| Frequency Selectivity | <0.013 Hz |
| Low‑Pass Filter Options | Three‑stage CIC, Integrate‑and‑Dump, or Bypass |
| Decimation Range | 1‑4096 (fixed) or adjustable via NCO |
| Package | 84‑lead PLCC |
| Internal AGC Loop | Provides output level stability |
The device can sample inputs up to 52 MSPS.
It is supplied in an 84‑lead PLCC package.
Yes, it supports parallel or serial output data formats.
An internal AGC loop maintains output level stability.