The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It supports a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided. For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an on-board ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quarter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter. The serial interface for 3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface.
The HSP43124 Serial I/O Filter is designed to off‑load filter processing from DSP microprocessors. It supports programmable FIR filters up to 256 taps, cascaded half‑band filters, and a two‑pin down‑conversion interface.
The device features a bidirectional 8‑bit serial interface for loading coefficients and configuration data, a multiplier for mix‑factor scaling, and is supplied in a 28‑lead SOIC package with RoHS‑compliant Pb‑free options.
| Clock Rate | 45 MHz |
|---|---|
| FIR Filter Length | 256 taps |
| Data Width | 24‑bit |
| Coefficient Width | 32‑bit |
| Half‑Band Filters | Up to 5 cascaded |
| Decimation Range | 1 – 256 |
| Down‑Conversion Interface | Two‑pin (Fs/4) |
| Mix‑Factor Multiplier | Supported |
| Package | SOIC 28‑LD (300 mil) |
The device supports up to 256 programmable FIR taps.
Up to five half‑band filters can be cascaded.
The filter engine operates at a 45 MHz clock rate.
It is supplied in a 28‑lead SOIC (300 mil) package.